1. Field of the Invention
The present invention relates to a semiconductor memory element, semiconductor memory device and control method therefore.
2. Prior Art
In the conventional art, non-volatile memory devices have been achieved such as flash EEPROM devices by utilizing MOSFET devices having floating gates and control gates. In such devices, information storage and readout are performed by utilizing the fact that the MOSFET threshold voltage changes when carriers accumulate on the floating gate. Polycrystalline silicon was generally utilized in the floating gate. Utilizing a MOSFET with floating gate allowed one bit of information to be stored for extended periods of time by use of only one transistor. A conventional structure and a contact-less cell structure are described in Nikkei Electronics, no. 444, pp. 151-157 (1988), as examples of flash EEPROM memory cell structures.
Technology of the conventional art relating to this invention is disclosed in K. Yanoetal, 1993 IEEE International Electron Devices Meeting, Digest of technical papers, pp. 541-545 and also in K. Yano et al, 1996 IEEE International Solid-State Circuits Conference, Digest of technical papers, pp. 266-267 and p. 458, describing single-electron memories utilizing polycrystalline silicon. In this technology, the channel which is an electrical path and a storage region to capture electrons are simultaneously formed of thin-film, polycrystalline silicon. Storage of information is performed by utilizing the change in threshold voltages when electrons are captured in the storage region. A feature of this method is that one bit is stored with the deposit of one electron. A smaller structure can be obtained, compared with a structure obtained by machining utilizing the crystal grains of polycrystalline silicon and the device of this method can also operate at room temperature.
In order to achieve the desired change in threshold voltage in flash EEPROM devices at carrier injection and drain (write, erase operation) to the floating gate, the memory state is monitored after application of a high voltage (or low voltage) and a verify operation is performed to once again apply a voltage to adjust the threshold values in cells where the desired threshold value was not obtained.
In the conventional art, technology for verify operations is disclosed in T. Tanaka et al. IEEE J. Solid-State Circuits, Vol. 29, No. 11, pp. 1366-1372 (1994) and in K. Kimura et al. IEICE Transactions on Electronics, Vol. E78-C No. 7, pp. 832-837 (1995).
Previous technology by the inventors of the present invention is disclosed in Japanese Patent Laid-open No. Hei 7-111295, No. Hei 8-288469, No. Hei 9-213822 and in Japanese Patent Laid-open No. Hei 9-213898.